The electronics industry continues to rely upon advances in semiconductor technology to realized higher-function devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
Many varieties of semiconductor devices are manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor field-effect transistors (MOSFET), such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, and CMOS combined with bipolar transistors, BiCMOS transistors. Such MOSFET devices include an insulating material between a conductive gate and silicon-like substrate; therefore, these devices are generally referred to as IGFETs (insulated-gate FET).
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions. In bipolar transistors, an active device generally includes emitter and collector regions and a base electrode to control operation of the transistor.
Furthermore, such devices may be digital or analog devices produced in a number of wafer fabrication processes, for example, CMOS, BiCMOS, Bipolar, etc. The substrates may be silicon, gallium arsenide (GaAs) or other substrate suitable for building microelectronic circuits thereon.
In some processes, both CMOS and bipolar transistors are fabricated on the same device so that the advantages of each technology may be realized. For example, integrated circuits used in wireless communication may use CMOS logic to control particular user-operations while the bipolar technology provides necessary RF components.
The following references provide background information on bipolar processing that may be integrated with a CMOS fabrication process; they are incorporated by reference in their entirety.
U.S. Pat. No. 5,340,753 (issued Aug. 23, 1994) titled, “Method for Fabricating Self-Aligned Epitaxial Base Transistor” of Bassous et al., relates to the fabrication of very small integrated bipolar transistors using double polysilicon deposition technology and more particularly, to self-aligned epitaxial base transistors formed by low temperature epitaxy.
U.S. Pat. No. 6,228,733 B1 (issued May 8, 2001) titled, “Non-Selective Epitaxial Deposition Technology” of Lee et al., relates to the general field of bipolar transistor manufacture with particular reference to the base layer.
U.S. Patent Application Publication US 2002/0132438 A1 (published Sep. 19, 2002) titled, “Epitaxial Base Bipolar Transistor with Raised Extrinsic Base” of Dunn et al., relates to bipolar transistors, and more particularly to an epitaxial base bipolar transistor having a raised extrinsic base and method of fabricating same.
RF performance of bipolar transistors is largely limited by parasitics. In combining bipolar and CMOS on a single substrate one has to minimize the parasitic capacitance between the collector and base (CCB) and emitter and base (CEB). Furthermore, there may be increased base resistance (RB-ext). Such parasitics negatively affect device performance.
There exists a continuous need to minimize the parasitic collector-base (CCB) and emitter-base (CEB) capacitance of a bipolar transistor and to minimize the base resistance RB-ext. Furthermore, the process should be compatible with CMOS recipes and not require too many additional steps.